1) Field of the Invention
The invention is in the field of Semiconductor Devices.
2) Description of Related Art
For the past several years, the performance of semiconductor devices, such as Metal Oxide Semiconductor Field-Effect Transistors (MOS-FETs), has been greatly enhanced by the incorporation of metal layers, e.g. the use of metal gate electrodes. In the drive for patterning ever-smaller device features, the importance of precisely patterning such metal layers has increased dramatically.
Conventional patterning techniques used to pattern metal layers in the presence of other layers in a semiconductor structure may detrimentally impact the other layers. For example, a photo-resist may erode if present during a conventional metal patterning process. Also, the formation of residues during a metal layer patterning process may obscure the patterning process and impact the quality of the metal feature that is formed. Thus, a method to pattern metal layers in a semiconductor structure is described herein.